The present invention relates to a semiconductor integrated circuit.
A semiconductor integrated circuit of FIG. 1 is conventionally proposed in order to reduce current consumption in the non-operating state of the semiconductor integrated circuit. Hereinafter, this semiconductor integrated circuit will be described.
Referring to FIG. 1, a PMOS (P-channel Metal Oxide Semiconductor) transistor 4 (hereinafter, simply referred to as xe2x80x9cPMOSxe2x80x9d) is connected between a power supply terminal 2 of an inverter circuit 1 and a power supply potential 7. An NMOS (N-channel Metal Oxide Semiconductor) transistor 5 (hereinafter, simply referred to as xe2x80x9cNMOSxe2x80x9d) is connected between a ground terminal 3 of the inverter circuit 1 and a ground potential 8. These transistors are manufactured with a greater threshold value (absolute value) than transistors in the inverter circuit 1. Therefore, when the inverter circuit 1 is in the non-operating state, the PMOS 4 and the NMOS 5 are turned OFF as shown in the figure. As a result, a current flowing into the inverter circuit 1 is limited by these transistors and the like, enabling reduction in current consumption in the non-operating state.
However, when PMOS 4 and the NMOS 5 are turned OFF, the inverter circuit 1 is rendered in a substantially open state as viewed from the power supply potential 7 and the ground potential 8 of the power supply terminal 2 and the ground terminal 3. Therefore, regardless of the potential of an input signal 6, the power supply terminal 2 and the ground terminal 3 transition toward the same potential by the current in the inverter circuit 1, and finally reach the same potential. As a result, the conventional semiconductor integrated circuit reduces current consumption in the non-operating state, but cannot hold a signal that is determined at an output terminal 9 in the operating state.
It is an object of the present invention to provide a semiconductor integrated circuit capable of reducing current consumption in the non-operating state and holding, even in the non-operating state, a signal determined in the operating state.
In order to achieve the above object, the present invention is made based on the following considerations: first, how an output signal is determined in the operating state of the semiconductor integrated circuit will be described. Thereafter, in what state the active elements of the circuit are required to be in order to hold the output signal determined in the operating state even in the non-operating state of the semiconductor integrated circuit will be described. Thereafter, the problems will be described which are encountered when the output signal determined in the operating state is held when the power supply potential is set to an extremely low value (a value that is commonly recognized to be too low to operate the transistors due to an extremely small operating current (at most several tens of nanoamperes)), as shown in FIGS. 4A, 4B. For example, the extremely low potential is a potential equal to or lower than a threshold value Vt (absolute value) of the transistors. Basic technology for solving such problems will also be described. The following discussion is given for an inverter circuit formed from a PMOS and an NMOS, a basic structure of the logic circuit.
FIG. 2A shows an inverter circuit formed from a PMOS 10 and an NMOS 11. State transition of the PMOS 10 and the NMOS 11 will be considered. It is herein assumed that a signal applied from a signal generator 13 to an input terminal 12 of the inverter circuit transitions from L level (ground potential level) to H level (power supply potential level). As shown in xe2x80x9cInitial Statexe2x80x9d in Table 1 below, a current In of the NMOS 11 (a current flowing from the drain terminal to the source terminal) is sufficiently greater than a current Ip of the PMOS 10 (a current flowing from the source terminal to the drain terminal) right after the input signal transitions from L level to H level. The power supply terminal as considered herein refers to a power supply potential that allows the inverter circuit to achieve a desired design operating speed in the operating state. The current In of the NMOS 11 is about a hundred times as large as the current Ip of the PMOS 10. Therefore, such a state is commonly described like xe2x80x9cthe NMOS 11 is ON and the PMOS 10 is OFFxe2x80x9d.
Since Ip less than  less than In in the initial state, a current flows out of a load capacitor 14. As a result, a connection terminal with the inverter circuit falls toward the ground potential, and finally reaches the final state in Table 1. In the final state, Ip is equal to In, and an output terminal of the inverter circuit is at L level. The reason why the output terminal transitions to L level is that a resistance value Rp from the source terminal to the drain terminal of the PMOS 10 is greater than a resistance value Rn from the drain terminal to the source terminal of the NMOS 11. Therefore, the output signal Vout1 in the final state is given by the following expression:
Vout1=Rn/(Rp+Rn)Vdd1xe2x86x920xe2x80x83xe2x80x83(1).
In other words, the output signal Vout1 transitions to L level in the final state. In the expression (1), Vdd1 is a first power supply potential, and Rn/Rp is approximated to zero. The output signal in the final state is thus determined by the resistance values Rp, Rn of the PMOS 10 and the NMOS 11. Hereinafter, considerations will be given by commonly used terms and expressions. Therefore, conductances Gp, Gn of the PMOS 10 and the NMOS 11 (the reciprocals of the resistance values Rp, Rn: 1/Rp, 1/Rn) are used instead of the resistance values Rp, Rn. The above description is given for the case where the input signal transitions from L level to H level. Table 1 also shows the initial state and the final state regarding transition from H level to L level. Since operation is the same as that described above, description thereof will be omitted.
Hereinafter, the meaning of the expression xe2x80x9cthe output signal is lostxe2x80x9d will be described. FIGS. 3A to 3F and FIGS. 4A, 4B show characteristics of the PMOS and the NMOS. In the figures, the abscissa indicates a voltage Vds between the drain terminal and the source terminal of the PMOS and the NMOS, and the ordinate indicates a current Id between the drain terminal and the source terminal of the PMOS and the NMOS. In order to show the characteristics of the PMOS and the NMOS in the first quadrant of the graph, the graphs were written on the following conditions: for the PMOS, the abscissa indicates a potential of the source terminal relative to the drain terminal and the ordinate indicates a current flowing from the source terminal to the drain terminal; and for the NMOS, the abscissa indicates a potential of the drain terminal relative to the source terminal and the ordinate indicates a current flowing from the drain terminal to the source terminal. The same applies to FIGS. 5A, 5B, 7 and 10 in order to show the characteristics of the PMOS and the NMOS in the first quadrant of the graph.
Curve Non in FIG. 3C represents current characteristics of the NMOS in the state of FIG. 3A. The gate terminal of the NMOS is connected to the drain terminal thereof. As shown by thick line in FIG. 3C, the current characteristics of the NMOS exhibit a profile close to a quadratic curve with decrease in voltage Vds on the abscissa. Curves Noff represent characteristics of the NMOS in the state of FIG. 3B. It is herein assumed that different fixed potentials Vg (i.e., Vg1, Vg2, Vg3) are applied to the gate terminal of the NMOS (Vg1 greater than Vg2 greater than Vg3). Each curve A, B, C of the current characteristics Noff has the same property. More specifically, provided that the potential Vds is the same, a greater current Id flows as a higher potential is applied to the gate terminal. However, when the voltage Vds is zero, the current Id is also zero regardless of the potential Vg of the gate terminal. In view of this, what characteristic curve will be obtained when a potential Vdd2 is applied to the gate terminal of the NMOS will now be described. It is herein assumed that the curve Non and the curve A (i.e., the curve that is obtained when the NMOS in the state of FIG. 3B and the first power supply potential Vdd1 is applied to the gate terminal as the gate potential Vg) are known in advance.
First, the point n21 where the voltage Vds becomes equal to the power supply potential Vdd2 is found along the current curve Non. This point represents the current Id in the state of FIG. 3A, and also corresponds to the state where the potential from the source terminal to the gate terminal of the NMOS in FIG. 3B is Vdd2. It is therefore understood that, the curve C extending through the point n21 is obtained when the gate terminal of FIG. 3B has a potential Vdd2. In this way, the characteristic curve of the NMOS having an arbitrary gate potential can be obtained. When Vdd2=0, the point of Vdd2=Vds=0 in the curve Non corresponds to the origin. Therefore, the characteristic curve of FIG. 3B matches the curve Non only at the origin (Vds, Id)=(0, 0) (which corresponds to the relation between curves Non and Noff and between curves Pon and Poff in FIG. 7.
The above description is given for the NMOS. Since the same description applies to the PMOS, detailed description thereof will be omitted. FIGS. 3D to 3F showing characteristics of the PMOS respectively correspond to FIGS. 3A to 3C.
FIGS. 4A, 4B are given for understanding of the state of the PMOS and the NMOS in the inverter circuit. FIG. 4B shows the same current characteristic curve (second current characteristics) Non as that of FIG. 3C. In FIG. 4B, the first power supply potential Vdd1 is a power supply voltage in the operating state of the inverter circuit. The first power supply voltage Vdd1 is supposed to be significantly different from the power supply voltage Vdd2, a power supply voltage in the non-operating state of the inverter circuit (Vdd2 less than xc2xcVdd1). However, the first power supply potential Vdd1 has the same qualitative property as that of the power supply potential Vdd2. Therefore, for better understanding, the first power supply potential Vdd1 is herein set to a value close to the second power supply potential Vdd2. Vdd1 is a power supply potential of the inverter circuit, and the power supply potential Vdd1 (corresponding to H level) is applied to the inverter circuit as an input signal. Since the output signal has a power supply potential Vdd1 in the initial state, a current Id corresponding to the power supply potential Vdd1 on the curve Non flows through the NMOS. On the other hand, the PMOS has a power supply potential Vdd1 at both the gate terminal and the source terminal. Therefore, it is commonly considered that a small current flows through the PMOS. Moreover, the PMOS is now in the state of FIG. 3E. Accordingly, as shown in FIG. 4B, the PMOS exhibits a property similar to that of the curve A in FIG. 3C, and therefore has characteristic curve Poff (first current characteristics). In the initial state, a current flowing through the PMOS is approximately equal to zero. The current in the initial state is given by the following expression:
Idp less than Idnxe2x80x83xe2x80x83(2)
It is therefore understood from the discussion about FIG. 2 and Table 1 that the output signal is at L level. The final state is approximately equivalent to the state of FIG. 4A, and is given by the following expression:
xe2x80x83Idp=Idn=Id1xe2x80x83xe2x80x83(3)
where Idp is a current Id of the PMOS, and Idn is a current Id of the NMOS. The PMOS is in the state p11, and the NMOS is in the state n12. The relation between the conductances Gp, Gn can be given by the following expression:
Gp less than Gnxe2x80x83xe2x80x83(4).
This relation matches the logic in Table 1. The conductances Gp, Gn are gradients (differential values) in the states p11, b12.
Hereinafter, how the output signal thus determined will become if the power supply potential is reduced to the potential Vdd2 will now be considered. The potential Vdd2 is lower than the potential at the intersection xcex1 where the curves Non, Poff cross each other. In other words, the relation between currents of the curves Non, Poff is reversed at the intersection xcex1. It is herein assumed that the power supply potential varies from the final state of Vdd1 to the final state of Vdd2 in a static or approximately static manner (the output signal is held during the fall of the power supply potential). In the final state of Vdd2, the PMOS is in the state p22, the NMOS is in the state n21, and
Idp=Idn=Id2xe2x80x83xe2x80x83(5)
Gp greater than Gnxe2x80x83xe2x80x83(6)
The output signal is at H level. When the power supply potential is Vdd2, H level at the input terminal of the inverter circuit is Vdd2. Therefore, the curve Non(Vdd2) in FIG. 4B represents characteristics in the case of Vg=Vdd2 in the state of FIG. 3B. It can be understood that, in view of the fact that the input signal of the inverter circuit is H level, the output signal at a power supply potential higher than the intersection xcex1 is different from that at a power supply potential lower than the intersection xcex1. This means that the output signal held at a potential higher than the intersection xcex1 was lost at a potential lower than the intersection xcex1.
The relation between the conductances of the PMOS and the NMOS is as follows: Gp is approximately equal to Gn at the intersection xcex1; Gp less than Gn at a potential Vds higher than the intersection xcex1; and Gp greater than Gn at a potential Vds lower than the intersection xcex1. The potential at the intersection xcex1 is important as a reference potential for determining high (H) level and low (L) level of the output signal of the inverter circuit in FIG. 4A. The conductance ratio between the PMOS and the NMOS at the intersection xcex1 is also important as a reference conductance ratio for determining H level and L level of the output signal of the inverter circuit in FIG. 4A.
In order to hold the output signal at a power supply potential lower than the potential at the intersection xcex1, the present invention proposes to shift the intersection xcex1 of the curves Non, Poff to the intersection xcex2, as shown in FIG. 5B. Unlike FIG. 4B, FIG. 5B mainly shows the potential region lower than the intersection xcex1 in order to illustrate a potential Vds lower than the intersection xcex1. One way to shift the intersection is to shift the curve Poff to the curve Poff(Vbp) as shown in FIG. 5B. The curve is shifted by setting the potential of the well terminal of the PMOS to a value higher than the potential of the source terminal thereof. By setting the potential Vbp of the well terminal to a prescribed value, the potential Vds at the intersection xcex2 becomes smaller than the power supply potential Vdd2. As a result, the inverter circuit can hold the output signal even at the power supply potential Vdd2. The PMOS is in the state p21 and the NMOS is in the state n22. The intersection may alternatively be shifted to the intersection xcex3 of FIG. 5B by setting the potential Vbn of the well terminal of the NMOS to a value higher than the potential of the source terminal. Alternatively, the intersection may be shifted to the intersection xcex4 of FIG. 5B by combining the above two methods as shown in FIG. 6.
Current consumption in the final state is Id1, Id2. It can be seen from FIG. 4B that the currents Id1, Id2 at the power supply potentials Vdd1, Vdd2 have the following relation:
Id1 greater than Id2xe2x80x83xe2x80x83(7).
In other words, the current consumption is reduced as the power supply potential is reduced.
The above description is given for the curves Non, Poff. Even if the ON/OFF states of the NMOS and the PMOS are reversed, the same discussion can be given about the intersection of curves Pon, Noff. Therefore, description thereof will be omitted.
The above description is given for the case where the input signal of the inverter circuit is at H level. The above discussion does not apply to the L-level input signal for the following reasons: in FIG. 7, curve Pon represents characteristics of the PMOS in the state corresponding to FIG. 3A, and curve Poff represents characteristics of the PMOS in the state corresponding to FIG. 3B. In the curve Poff, the gate terminal has a power supply potential. Moreover, curve Non represents characteristics of the NMOS in the state of FIG. 3A, and curve Noff represents characteristics of the NMOS in the state of FIG. 3B. In the curve Noff, the gate terminal has a ground potential. From the discussion of FIGS. 3A to 3F, the curves Pon, Poff cross only at the following point in the first quadrant of the graph:
(Vds, Id)=(0, 0)xe2x80x83xe2x80x83(8).
The same applies to the curves Non, Noff. Accordingly, if the curves Non, Poff has an intersection, the following relations are satisfied:
Pon greater than Non greater than Noff
Pon greater than Poff greater than Noffxe2x80x83xe2x80x83(9).
In other words, if the curves Non, Poff has an intersection, the following relation is satisfied:
Pon greater than Noffxe2x80x83xe2x80x83(10).
The above expressions (9), (10) represent the relation between the curves. In other words, the inequality signs in the expressions (9), (10) represent the relation between current values Id at the same potential Vds. For example, the expression (10) indicates that the current Id on the curve Pon is always greater than that on the curve Noff at the same potential Vds. Since the curves Pon, Noff cross only at the point given by the expression (8), the inverter circuit would hold the output signal as long as the power supply potential is greater than the ground potential. Although the above description is given for the case where the curves Non, Poff have an intersection, the same description applies to the case where the curves Pon, Noff have an intersection. Therefore, description thereof will be omitted. Which of the curves Non, Poff and the curves Pon, Noff have an intersection depends on the circuit structure, circuit design and transistor characteristics or transistor design.
A means for allowing the inverter circuit to hold the output signal with low current consumption in the non-operating state has been described above. However, this proposed means may be implemented in view of a gate leak current and a junction leak current. The gate leak current is a current flowing from the gate terminal of a MOS transistor to another terminal (source terminal, drain terminal, well terminal) thereof. The junction leak current is a current flowing from the well terminal to the source terminal and the drain terminal. Even when such currents are significant for holding the output signal, the inverter circuit can hold the output signal at a power supply potential Vdd2 by setting a potential in a prescribed manner.
FIG. 8 shows a circuit including two inverter circuits each formed from a PMOS and an NMOS. In this circuit, an input terminal of one inverter circuit is connected to an output terminal of the other inverter circuit, and an input terminal of the other inverter circuit is connected to an output terminal of one inverter circuit. This circuit is a basic component of a flip-flop circuit (hereinafter, referred to as xe2x80x9cFxe2x80x94F circuitxe2x80x9d) and an SRAM (Static Random Access Memory, in particular, a six-transistor SRAM). It is herein assumed that, when the source terminal of the PMOS has a potential Vdd2, the inverter circuit 15 holds L level as an output signal and the inverter circuit 16 holds H level as an output signal. This will be described based on the inverter circuit 15. In the figure, i denotes a current flowing through the inverter circuits 15, 16. For each current, the first letter in the subscript denotes the start point of the current, and the second letter denotes the end point of the current. The third letter is xe2x80x9cpxe2x80x9d for the current of the PMOS and xe2x80x9cnxe2x80x9d for the current of the NMOS, and the fourth (last) letter is xe2x80x9caxe2x80x9d for the current of the inverter circuit 15 and xe2x80x9cbxe2x80x9d for the current of the inverter circuit 16. For example, isgpa is a current flowing from the source terminal to the gate terminal of the PMOS in the inverter circuit 15.
The currents relating to the potential of the output signal of the inverter circuit 15 are as follows:
for the inverter circuit 15,
isdpa, igdpa, ibdpa, igdna, idbna, idsnaxe2x80x83xe2x80x83(11);
and
for the inverter circuit 16,
isgpb, idgpb, idgnb, igsnbxe2x80x83xe2x80x83(12).
It is clearly understood that one end of each of the above currents has a starting point or end point at the output terminal of the inverter circuit 15. In order to hold the output signal at L level, a current must flow into the output terminal of the inverter circuit 15 (i.e., the inverter current 15 must receive a current at the output terminal), and
io less than 0xe2x80x83xe2x80x83(13).
(In order to hold the output signal at H level, a current must flow out of the output terminal of the inverter circuit 15 (i.e., the inverter circuit 15 must supply a current from the output terminal), and io greater than 0). Accordingly, the output signal can be held if the following condition is satisfied:
io=isdpa+igdpa+ibdpa+igdnaxe2x88x92idsnaxe2x88x92idbnaxe2x88x92isgpbxe2x88x92idgpbxe2x88x92idgnb+igsnb less than 0xe2x80x83xe2x80x83(14).
Every current is based on the potential relation between the starting point and the end point, has a positive value. The expression (14) can be rewritten as follows:
isdpa+(igdpa+ibdpa+igdna+igsnb) less than idsna+(idbna+isgpb+idgpb+idgnb)xe2x80x83xe2x80x83(15)
In the expression (15), the currents in parentheses indicate those which cannot be controlled by setting the potential of the well terminal, unlike the currents that are not in parentheses (i.e., isdpa, idsna). The current isdpa is reduced by increasing the potential of the well terminal of the PMOS. Accordingly, if the expression (15) is not satisfied, the potential of the well terminal of the PMOS need only be set to a higher value. Moreover, the current idsna is increased by increasing the potential of the well terminal of the NMOS. Accordingly, the expression (15) can also be satisfied by this method. It should be understood that the above two methods may be combined. The above description is given for the state where the inverter circuit 15 outputs L level. It is appreciated from the discussion of FIG. 7 that H level can be easily held when the inverter circuit 15 outputs H level. Therefore, detailed description thereof will be omitted.
In view of the above considerations, according to the present invention, data in the operating state of the semiconductor integrated circuit is held in the non-operating state by setting a power supply voltage to a value much smaller than the power supply voltage in the operating state while maintaining the relation between conductances in the operating state of transistors of the semiconductor integrated circuit.
More specifically, according to a first aspect of the present invention, a semiconductor integrated circuit has a power supply terminal, a ground terminal, and an output terminal, and includes a transistor in a component. The semiconductor integrated circuit includes a conductance regulating means having a control terminal for controlling at least one of a conductance between the power supply terminal and the output terminal and a conductance between the ground terminal and the output terminal. In an operating state of the semiconductor integrated circuit, a potential of the power supply terminal is set to a first power supply terminal. In a non-operating state of the semiconductor integrated circuit, the potential of the power supply terminal is set to a second power supply potential lower than the first power supply potential, and the conductance regulating means sets a potential of the control terminal to a prescribed value so as to regulate at least one of the conductance between the power supply terminal and the output terminal and the conductance between the ground terminal and the output terminal in response to setting of the power supply terminal to the second power supply potential.
Preferably, the second power supply potential is equal to or less than a quarter of the first power supply potential.
Preferably, the second power supply potential is equal to or less than a threshold potential of the transistor of the semiconductor integrated circuit.
Preferably, the conductance regulating means is a first MOS (Metal Oxide Semiconductor) transistor provided between the power supply terminal and the output terminal or a second MOS transistor provided between the ground terminal and the output terminal, and regulates a conductance between a source terminal and a drain terminal of the MOS transistor. The control terminal is a well terminal of the first or second MOS transistor.
Preferably, a conductance ratio is defined as a ratio between the conductance between the power supply terminal and the output terminal and the conductance between the ground terminal and the output terminal. A boundary potential is defined as a reference potential for determining whether an output signal from the output terminal is at high level (H level) or low level (L level). A boundary ratio is defined as the conductance ratio at the boundary potential. When the conductance ratio is in one of two regions above and below the boundary ratio in the operating state of the semiconductor integrated circuit where the potential of the power supply terminal is set to the first power supply potential, the second power supply potential to which the power supply terminal is set in the non-operating state of the semiconductor integrated circuit is a potential that causes the conductance ratio to shift to the other region. The conductance regulating means regulates the potential of the control signal so that the conductance ratio remains in the one region without shifting to the other in the non-operating state of the semiconductor integrated circuit.
Preferably, first current characteristics are defined as characteristics of a current flowing between the source terminal and the drain terminal of one of the first and second MOS transistors when a potential of a gate terminal of the MOS transistor is equal to that of the source terminal thereof. Second current characteristics are defined as characteristics of a current flowing between the drain terminal and the source terminal of the other MOS transistor when a potential of the gate terminal of the other MOS transistor is equal to that of the drain terminal thereof. A first current value and a second current value are defined as current values of the first and second current characteristics which are obtained when a potential from the drain terminal to the source terminal of the first MOS transistor is equal to a potential from the source terminal to the drain terminal of the second MOS transistor. The second power supply potential to which the power supply terminal is set in the non-operating state of the semiconductor integrated circuit is determined so that a relation between the first and second current values in the non-operating state is the same as or opposite to that between the first and second current values in the operating state of the semiconductor integrated circuit.
Preferably, first current characteristics are defined as characteristics of a current flowing between the source terminal and the drain terminal of one of the first and second MOS transistors when a potential from the source terminal to a gate terminal of the MOS transistor is equal to a threshold potential. Second current characteristics are defined as characteristics of a current flowing between the drain terminal and the source terminal of the other MOS transistor when a potential of the gate terminal of the other MOS transistor is equal to that of the drain terminal thereof. A first current value and a second current value are defined as current values of the first and second current characteristics which are obtained when a potential from the drain terminal to the source terminal of the first MOS transistor is equal to a potential from the source terminal to the drain terminal of the second MOS transistor. A second potential to which the power supply terminal is set in the non-operating state of the semiconductor integrated circuit is determined so that a relation between the first and second current values in the non-operating state is the same as or opposite to that between the first and second current values in the operating state of the semiconductor integrated circuit.
Preferably, the MOS transistor provided between the power supply terminal and the output terminal is a PMOS transistor, and the MOS transistor provided between the ground terminal and the output terminal is an NMOS transistor.
According to a second aspect of the present invention, a semiconductor integrated circuit has a power supply terminal, a ground terminal, and an output terminal and includes a transistor in a component. The semiconductor integrated circuit includes a current regulating means having a control terminal for controlling a supplied current supplied from the power supply terminal through the output terminal to a load connected to the output terminal, or a received current flowing from the load through the output terminal to the ground terminal. In an operating state of the semiconductor integrated circuit, a potential of the power supply terminal is set to a first power supply terminal. In a non-operating state of the semiconductor integrated circuit, the potential of the power supply terminal is set to a second power supply potential lower than the first power supply potential, and a potential of the control terminal of the current regulating means is set to a prescribed potential so as to regulate at least one of the supplied current and the received current in response to setting of the power supply terminal to the second power supply potential.
Preferably, the control terminal of the current regulating means is set to a prescribed potential so that a direction of a current flowing between the output terminal and the load in the non-operating state of the semiconductor integrated circuit matches a direction of a current flowing between the output terminal and the load in the operating state of the semiconductor integrated circuit.
According to a third aspect of the present invention, a semiconductor integrated circuit includes a PMOS transistor having its source terminal connected to a power supply, and an NMOS transistor having its source terminal grounded, its drain terminal connected to a drain terminal of the PMOS transistor and serving as an output terminal, and its gate terminal connected to a gate terminal of the PMOS transistor. A potential of the power supply is set to a first potential in an operating state of the semiconductor integrated circuit, and set to a second potential lower than the first potential in a non-operating state of the semiconductor integrated circuit. In the non-operating state of the semiconductor integrated circuit, a well terminal of at least one of the PMOS transistor and the NMOS transistor is set to a prescribed potential so as to regulate a conductance between the drain terminal and the source terminal of the MOS transistor in response to setting of the power supply to the second potential.
Preferably, a conductance ratio is defined as a ratio between the conductance between the source terminal and the drain terminal of the PMOS transistor and the conductance between the drain terminal and the source terminal of the NMOS transistor. A boundary potential is defined as a reference potential for determining whether an output signal from the output terminal is at high level (H level) or low level (L level). A boundary ratio is defined the conductance ratio at the boundary potential. When the conductance ratio is in one of two regions above and below the boundary ratio in the operating state of the semiconductor integrated circuit where a potential of a power supply terminal is set to a first power supply potential, a second power supply potential to which the power supply terminal is set in the non-operating state of the semiconductor integrated circuit is a potential that causes the conductance ratio to shift to the other region. The well terminal of at least one of the PMOS transistor and the NMOS transistor is set to a prescribed potential so that the conductance ratio remains in the one region without shifting to the other in the non-operating state of the semiconductor integrated circuit.
Preferably, the second potential to which the power supply is set in the non-operating state of the semiconductor integrated circuit is either a potential that eliminates a current flowing between the output terminal and a load connected thereto or a potential that reverses a direction of the current flowing between the output terminal and the load in the non-operating state from that of a current flowing therebetween in the operating state of the semiconductor integrated circuit. The prescribed potential to which the well terminal is set is either a potential that does not eliminate a current flowing between the output terminal and the load in the non-operating state of the semiconductor integrated circuit or a potential that does not reverse a direction of the current flowing between the output terminal and the load in the non-operating state from that of a current flowing therebetween in the operating state of the semiconductor integrated circuit.
According to a fourth aspect of the present invention, a semiconductor integrated circuit includes a first PMOS transistor, a second PMOS transistor, a first NMOS transistor and a second NMOS transistor. The first PMOS transistor has its source terminal connected to a power supply. The first NMOS transistor has its source terminal grounded, its drain terminal connected to a drain terminal of the first PMOS transistor and serving as a first output terminal, and its gate terminal connected to a gate terminal of the first PMOS transistor and serving as a first input terminal. The second PMOS transistor has its source terminal connected to the power supply. The second NMOS transistor has its source terminal grounded, its drain terminal connected to a drain terminal of the second PMOS transistor and serving as a second output terminal, and its gate terminal connected to a gate terminal of the second PMOS transistor and serving as a second input terminal. The first output terminal is connected to the second input terminal, and the second output terminal is connected to the first input terminal. A potential of the power supply is set to a first potential in an operating state of the semiconductor integrated circuit, and set to a second potential lower than the first potential in a non-operating state of the semiconductor integrated circuit. In the non-operating state of the semiconductor integrated circuit, a well terminal of at least one of the first and second PMOS transistors and a well terminal of at least one of the first and second NMOS transistors are set to a prescribed potential so as to regulate a conductance between the drain terminal and the source terminal of the MOS transistors in response to setting of the power supply to the second potential.
Preferably, the prescribed potential to which the well terminals of the first and second PMOS transistors are set in the non-operating state of the semiconductor integrated circuit is higher than the second potential. The prescribed potential to which the well terminals of the first and second NMOS transistors are set in the non-operating state of the semiconductor integrated circuit is higher than a ground potential.
Preferably, a conductance ratio is defined as either a ratio between a conductance between the source terminal and the drain terminal of the first PMOS transistor and a conductance between the drain terminal and the source terminal of the first NMOS transistor or a ratio between a conductance between the source terminal and the drain terminal of the second PMOS transistor and a conductance between the drain terminal and the source terminal of the second NMOS transistor. A boundary potential is defined as a reference potential for determining whether an output signal from the first and second output terminals is at high level (H level) or low level (L level), and a boundary ratio is the conductance ratio at the boundary potential. When the conductance ratio is in one of two regions above and below the boundary ratio in the operating state of the semiconductor integrated circuit where a potential of the power supply is set to the first potential, the second potential to which the power supply is set in the non-operating state of the semiconductor integrated circuit is a potential that causes the conductance ratio to shift to the other region. The prescribed potential to which the well terminal is set is determined so that the conductance ratio remains in the one region without shifting to the other in the non-operating state of the semiconductor integrated circuit.
Preferably, the second potential to which the power supply is set in the non-operating state of the semiconductor integrated circuit is lower than an absolute threshold potential of at least one of the first and second PMOS transistors and at least one of the first and second NMOS transistor.
Preferably, a first conductance is defined as a conductance from the source terminal to the drain terminal of one of the first PMOS transistor and the first NMOS transistor which is obtained when a potential from the source terminal to the gate terminal of the MOS transistor is a threshold potential thereof. A second conductance is defined as a conductance from the drain terminal to the source terminal of the other MOS transistor which is obtained when a potential of the gate terminal of the other MOS transistor is equal to that of the drain terminal thereof. The second potential to which the power supply is set in the non-operating state of the semiconductor integrated circuit is determined so that a relation between the first and second conductances in the non-operating state is the same as or opposite to that between the first and second conductances in the operating state of the semiconductor integrated circuit when a potential applied to the first conductance is equal to that applied to the second conductance.
Preferably, the first conductance is a conductance from the source terminal to the drain terminal of one of the first PMOS transistor and the second NMOS transistor which is obtained when a potential of the source terminal of the one MOS transistor is equal to that of the gate terminal thereof, rather than when a potential from the source terminal to the gate terminal of the one MOS transistor is a threshold potential thereof.
Preferably, the second potential to which the power supply is set in the non-operating state of the semiconductor integrated circuit is either a potential that eliminates a current flowing between the first output terminal and the second input terminal in the non-operating state or a potential that reverses a direction of the current flowing between the first output terminal and the second input terminal in the non-operating state from that of a current flowing therebetween in the operating state of the semiconductor integrated circuit. The potential to which the well terminal of the MOS transistor is set is either a potential that does not eliminate a current flowing between the first output terminal and the second input terminal in the non-operating state of the semiconductor integrated circuit or a potential that does not reverse a direction of the current flowing between the first output terminal and the second input terminal in the non-operating region from that of a current flowing therebetween in the operating state of the semiconductor integrated circuit.
Preferably, the semiconductor integrated circuit further includes a first switch means provided between the first input terminal and a first signal line to which a recorded signal is applied, and a second switch means provided between the second input terminal and a second signal line to which an inverted signal of the recorded signal is applied. The semiconductor integrated circuit forms a static random access memory.
Preferably, the control terminal is a gate terminal of the first or second MOS transistor rather than the well terminal of the first or second MOS transistor.
According to a fifth aspect of the present invention, a semiconductor integrated circuit includes a first signal processing means, and a second signal processing means. A relation between potentials of an input signal and an output signal of the second signal processing means is opposite to that of the first signal processing means. An output signal of the first signal processing means is applied to an input terminal of the first signal processing means through the second signal processing means. Each of the first and second signal processing means has a power supply terminal, a ground terminal, and an output terminal, and includes a transistor in a component, and a conductance regulating means having a control terminal for controlling at least one of a conductance between the power supply terminal and the output terminal and a conductance between the ground terminal and the output terminal. In an operating-state of the semiconductor integrated circuit, a potential of the power supply terminal is set to a first power supply potential. In a non-operating state of the semiconductor integrated circuit, the potential of the power supply terminal is set to a second power supply potential lower than the first power supply potential, and a potential of the control terminal of the conductance regulating means is set to a prescribed value so as to regulate at least one of the conductance between the power supply terminal and the output terminal and the conductance between the ground terminal and the output terminal in response to setting of the power supply terminal to the second power supply potential.
Preferably, the second power supply potential is equal to or less than a quarter of the first power supply potential.
Preferably, the second power supply potential is equal to or less than a threshold potential of at least one of transistors in the semiconductor integrated circuit.
Preferably, the conductance regulating means is a first MOS transistor provided between the power supply terminal and the output terminal or a second MOS transistor provided between the ground terminal and the output terminal, and regulates a conductance between a source terminal and a drain terminal of the MOS transistor. The control terminal is a well terminal of the first or second MOS transistor.
Preferably, a conductance ratio is defined as a ratio between the conductance between the power supply terminal and the output terminal and the conductance between the ground terminal and the output terminal. A boundary potential is defined as a reference potential for determining whether an output signal from the output terminal is at high level (H level) or low level (L level). A boundary ratio is defined as the conductance ratio at the boundary potential. When the conductance ratio is in one of two regions above and below the boundary ratio in the operating state of the semiconductor integrated circuit where the potential of the power supply terminal is set to the first power supply potential, the second power supply potential to which the power supply terminal is set in the non-operating state of the semiconductor integrated circuit is a potential that causes the conductance ratio to shift to the other region. The conductance regulating means regulates the potential of the control signal so that the conductance ratio remains in the one region without shifting to the other in the non-operating state of the semiconductor integrated circuit.
Preferably, first current characteristics are defined as characteristics of a current flowing between the source terminal and the drain terminal of one of the first and second MOS transistors when a potential of a gate terminal of the MOS transistor is equal to that of the source terminal thereof. Second current characteristics are defined as characteristics of a current flowing between the drain terminal and the source terminal of the other MOS transistor when a potential of the gate terminal of the other MOS transistor is equal to that of the drain terminal thereof. A first current value and a second current value are defined as current values of the first and second current characteristics which are obtained when a potential from the drain terminal to the source terminal of the first MOS transistor is equal to a potential from the source terminal to the drain terminal of the second MOS transistor. A second potential to which the power supply terminal is set in the non-operating state of the semiconductor integrated circuit is determined so that a relation between the first and second current values in the non-operating state is the same as or opposite to that between the first and second current values in the operating state of the semiconductor integrated circuit.
Preferably, first current characteristics are defined as characteristics of a current flowing between the source terminal and the drain terminal of one of the first and second MOS transistors when a potential from the source terminal to a gate terminal of the MOS transistor is equal to a threshold potential. Second current characteristics are defined as characteristics of a current flowing between the drain terminal and the source terminal of the other MOS transistor when a potential of the gate terminal of the other MOS transistor is equal to that of the drain terminal thereof. A first current value and a second current value are defined as current values of the first and second current characteristics which are obtained when a potential from the drain terminal to the source terminal of the first MOS transistor is equal to a potential from the source terminal to the drain terminal of the second MOS transistor. A second potential to which the power supply terminal is set in the non-operating state of the semiconductor integrated circuit is determined so that a relation between the first and second current values in the non-operating state is the same as or opposite to that between the first and second current values in the operating state of the semiconductor integrated circuit.
Preferably, the MOS transistor provided between the power supply terminal and the output terminal is a PMOS transistor, and the MOS transistor provided between the ground terminal and the output terminal is an NMOS transistor.
According to a sixth aspect of the present invention, a semiconductor integrated circuit includes a first signal processing means, and a second signal processing means. A relation between potentials of an input signal and an output signal of the second signal processing means is opposite to that of the first signal processing means. An output signal of the first signal processing means is applied to an input terminal of the first signal processing means through the second signal processing means. Each of the first and second signal processing means has a power supply terminal, a ground terminal, and an output terminal, and includes a transistor in a component, and a current regulating means having a control terminal for controlling a supplied current supplied from the power supply terminal through the output terminal to a load connected to the output terminal, or a received current flowing from the load through the output terminal to the ground terminal. In an operating state of the semiconductor integrated circuit, a potential of the power supply terminal is set to a first power supply terminal. In a non-operating state of the semiconductor integrated circuit, the potential of the power supply terminal is set to a second power supply potential lower than the first power supply potential, and a potential of the control terminal of the current regulating means is set to a prescribed potential so as to regulate at least one of the supplied current and the received current in response to setting of the power supply terminal to the second power supply potential.
Preferably, the control terminal of the current regulating means is set to a prescribed potential so that a direction of a current flowing between the output terminal and the load in the non-operating state of the semiconductor integrated circuit matches a direction of a current flowing between the output terminal and the load in the operating state of the semiconductor integrated circuit.
According to a seventh aspect of the present invention, a semiconductor integrated circuit includes a first signal processing means, and a second signal processing means receiving an output signal of the first signal processing means at its input terminal. The second signal processing means includes a boundary potential changing means capable of changing, by using a potential of a control terminal, a boundary potential for determining whether an output signal from an output terminal is at high level (H level) or low level (L level). Each of the first and second signal processing means has a power supply terminal and a ground terminal. The power supply terminal is set to a first power supply potential in an operating state of the semiconductor integrated circuit, and set to a second power supply potential lower than the first power supply potential in a non-operating state of the semiconductor integrated circuit. When an output potential of the first signal processing means is in one of two regions above and below the boundary potential of the second signal processing means in the operating state of the semiconductor integrated circuit, the potential of the control terminal is determined so that the boundary potential changing means causes the output potential of the first signal processing means to remain in the one region without shifting to the other in the non-operating state of the semiconductor integrated circuit.
Preferably, the semiconductor integrated circuit includes boundary potential changing means for changing the boundary potential by using a potential of the power supply terminal, rather than the boundary potential changing means for changing the boundary potential by using a potential of the control terminal.
Preferably, the semiconductor integrated circuit includes boundary potential changing means for changing the boundary potential by using a potential of the ground terminal, rather than the boundary potential changing means for changing the boundary potential by using a potential of the control terminal.
As has been described above, the semiconductor integrated circuit of the present invention may be applied not only to an inverter but also to static circuits such as SRAM, Fxe2x80x94F circuit, NAND circuit and NOR circuit, dynamic circuits and the like. According to the present invention, the power supply potential can be set to an extremely low value in the non-operating state of the circuit, and desirably set to a value lower than a threshold voltage of a transistor. As a result, reduction in power consumption can be achieved. Moreover, by setting a well terminal of at least one of the NMOS transistor and the PMOS transistor to a prescribed potential, the data held in the operating state of the circuit can be held even in the non-operating state.